Federal Bid

Last Updated on 31 Jan 2025 at 3 PM
Combined Synopsis/Solicitation
Washington District of columbia

Wafer Grinder and CMP Tools

Solicitation ID N0017325QMB04
Posted Date 31 Jan 2025 at 3 PM
Archive Date 01 Mar 2025 at 5 AM
NAICS Category
Product Service Code
Set Aside Total Small Business (SBA) Set-Aside (FAR 19.5)
Contracting Office Naval Research Laboratory
Agency Department Of Defense
Location Washington District of columbia United states 20375

See attached combined Synopsis/Solicitation and System Specifications. 

Note; The Government is accepting offers for both new and refurbished hardware. Contractors response needs to specify whether proposing new or refurbished.

Amendment #1 extends the due date for receipt of offers from 2/7/2025 to 2/14/2025

Amendment #2 responds to a question and posts a revised combined Synopsis/Solicitation changing the due date for offers to 2/14/2025.

Q. Regarding the RFQ for grind and CMP tools for Silicon Carbide – does the NRL intend to provide wafers for potential contractors to perform demonstrations, or are you just looking for data from previous demonstrations?

R. NRL will provide wafers for potential contractors to perform the demonstrations.

Amendment # 3 respond to following questions:

Q.   Is NRL looking for automated functions or semi-automatic? Is the purpose for R&D or production?

A. Semi-automatic functions are acceptable. The purpose of the tools is for R&D.

Q. Few machines automatically move from coarse grind to fine grind. Does NRL require high production or are they looking to do

wafers one at a time?

A. One wafer at a time.

Amendment #4 Respond to questions;

For bonded wafers, what is the incoming total wafer stack thickness?
Our standard thickness gauge can measure up to 1,800um. If the wafer it thicker than that, we can upgrade to 2.7mm IPG.

A. The total wafer stack thickness will be approx. 700 – 750 um

  1. SiC wafers have Si plane and C plane. If you could confirm which side to grind/polish, 
  2.  Which plane (Si or C plane) will you polish?

In answer to 1 and 2 above with regard to single SiC wafers:

  1. For single SiC wafers, the Si- and/or C-planes will need to be ground and/or polished in order to achieve the bow and TTV specs

b)    For bonded SiC/SiO2/Si stacks, the C-face of the SiC wafer will be ground and polished

c)   For bonded SiC/SiO2/SiC stacks, the exterior faces will be C-plane and at least one face will need to be ground and polished. The other SiC surface may need to be ground/polished in order to meet the bow and TTV specs

  1.  Are wafers single crystal or polycrystal?

Single crystal

Just for confirmation a multi-stage filtration system shall filter particles up to 0.1 μm in the waste water from the grinding tool at flow rates up to 12 gpm " in the Specifications => This is waste water from the grinder, correct?

Yes, correct, the waste water is from the grinder

Bid Protests Not Available

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