Central Design Parameters
MTCA.4 (µTCA for Physics Implementation) •
4 lane PCI Express Connectivity •
10 Channels 125 MS/s 16-bit ADC •
10 MS/s to 125 MS/s Per Channel Sampling Speed •
AC and DC Input Stage •
Internal, Front Panel, RTM and Backplane Clock Sources •
Two 16-bit DACs for Fast Feedback Implementation •
High Precision Clock Distribution Circuitry •
Programmable Delay of Dual Channel Digitizer Groups •
Gigabit Link Port Implemenation to Backplane •
Twin SFP Card Cage for High Speed System Interconnects •
Virtex 5 FPGA •
32 MSample Memory per Channel •

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